A Method for Accelerating Convolutional Neural Networks Based on FPGA

Convolutional neural networks (CNNs) have achieved notable success in the field of computer vision, ranging from image classification to object detection. However, characteristics of intensive multiplication computing, large-scale parameters and resource consuming enormously restrict its application in embedded devices. In this paper, we propose a method that accelerates a target CNN module based on FPGA, and the network we used to demonstrate is LeNet-5. Firstly, the LeNet-5 module will be pruned using Dynamic Network Surgery. Secondly, we quantize the parameters to 8-bits in the pruned network by the quantization scheme called Incremental Network Quantization, and recode it to 5-bits for shift operation. Finally, we develop a model-friendly parallel hardware accelerator with 8-bits fixed-point precision using Verilog HDL codes, and integrate it to a SOC system. By converting multiplication operations to shift operations, we design a parallel LUT-based hardware accelerator with no DSP resources utilized. Processed by Xilinx ZC702 FPGA at 100MHz clock, this implementation reaches a peak performance of 33.6 GMACS with only 1.758 W of total on-chip power, and obtains 98.9% accuracy target 10000 images of MNIST test set.