Surge Energy Robustness of GaN Gate Injection Transistors

An essential robustness of power devices is the capability to safely withstand surge energy, which is typically characterized in an unclamped inductive switching (UIS) condition. Si and SiC power MOSFETs can dissipate surge energy through avalanching. However, GaN high-electron-mobility-transistors (HEMTs) have no or minimal avalanche capability. Prior works reported controversial interpretations of the behaviors of GaN HEMTs in UIS tests. This work, for the first time, clarifies the surge-energy withstand process of a mainstream enhancement-mode GaN HEMT, the GaN gate injection transistor (GIT). Different from Si and SiC MOSFETs, GaN GITs are shown to withstand the surge energy through a resonant energy transfer from device output capacitance back into the load inductor, followed by the device reverse conduction and inductor discharging. Almost no energy is dissipated in the device during this resonant withstand process. The failure mechanism of GaN GITs has also been identified. It was found that the surge-energy robustness of GaN GITs is almost solely determined by their transient overvoltage capability. Failure analysis and mixed-mode TCAD simulation confirm that the device failure location is consistent with the peak electric field location at the peak overvoltage transient. These results suggest the avalanche energy, a widely used JEDEC standard for the robustness of Si and SiC power MOSFETs which represents the device capability to resistively dissipate energy without thermal runaway, may not be a parameter that can directly represent the surge energy robustness of GaN HEMTs. In addition, benefited from the sub-50 ns overvoltage pulse created by the UIS test, the electrical breakdown location of hybrid-drain GIT was experimentally verified for the firs time.