FPGA Realization of Hardware-Flexible Parallel Structure FIR Filters Using Combined Systolic Arrays

In order to realize the flexibility of real-time digital signal processing system. This paper presents a novel parallel Frequency Impulse Response (FIR) filter structure based on Combined Systolic Arrays (CSAs). CSAs are associated with the polyphase decomposition of parallel FIR structure which can suitable for dedicate arithmetic – Convolution in a real-time system. Based on Look Up Tables (LUTs) in Field Programmable Gate Array (FPGA), it is flexible to configure different coefficient order and path of parallel as the cascade characteristic of the CSAs. The proposed structure is validated via an FIR bandpass filter and a fractional delay filter in an FPGA (Xilinx, XC7325T). The implementation results indicate that the proposed structure can guarantee the high efficiency of the real-time system and realize the Hardware-Flexible.