Design Optimization for a GaN FET-based Three-level Synchronous Buck Converter

Multi-level buck converters offer the benefits of improved efficiency and power density. GaN FETs with their low loss and small physical size further enhance these advantages. However, an optimal design of a GaN-based multilevel converter is nontrivial. Challenges lie in an optimal layout with low parasitic inductance that is critical for GaN switching performance to achieve high efficiency and power density, and the complexity of the gate drive circuit that increases with the number of voltage levels. On top of that, the control of the multi-level converter must properly address the start-up and flying capacitor voltage management. This paper presents design optimization for a GaN FET-based three-level converter. A simplified bootstrap circuit for the gate drivers, start-up scheme, and flying capacitor voltage balancing control will be covered. Layout guidelines will be given based on an analysis of the current commutation loops. Test results of a 48 V to 12-20 V, 10 A three-level converter will be given to verify the proposed design. The full load efficiency is 97.5% and 96.3% efficiency for 20 V and 12 V output voltages, respectively.