Test Logic Insertion for Optimization of Testing Parameters on Lower Technology Node

The complexity and gate counts on chips is growing rapidly on networking application chips, because of s maller lithographic nodes. Design for testability (DFT) ensures no manufacturing defect on the VLS I fabricated chips. Structured DFT approaches like scan methodology, BIST, MBIST ensure quality. Nowadays, DFT itself face critical challenge due to node scaling and it affects the density of the fabricated chip. In this paper, to optimize the parameters on the 28nm technology node, like test time, test coverage, power dissipation, the area should be analysed. This is the major concern of DFT for ASIC chip designing process.