Multi-bit Upset Mitigation with Double Matrix Codes in Memories for Space Applications

As transistor size shrinks due to CMOS scaling (namely the node is 65 nm or less), multi-bit upset (MBU) becomes an increasingly important problem. The mostly adopted error-detection-and-correction codes, including the parity code, the Hamming code and the matrix code have the limitation of bit numbers of detection and correction. An emergent technique is required to deal with the cases of more than two-bit upset errors. In this paper, we propose a double matrix code to address this issue. The double matrix code, which is implemented by two-dimensional matrix codes and logic interleaving, is taken one step further for the sake of the enhancement of the correction capability of memories. The encoding-and-decoding procedure is described in detail. The results of fault-injection experiments and the discussion are also given. The tested results show that the proposed scheme can improve the reliability of memories. Meanwhile, the proposed scheme can obtain the best results of the mean-time-to-failure (MTTF). The cost of the proposed technique is less than traditional methods, while the fault coverage is approximately equal to the complex Bose-Chaudhuri-Hocquenghem (BCH) codes. Thus, the proposed scheme can be applied into radiation hardness of general SRAMs for space applications.