Implementation and Extension of Bit Manipulation Instruction on RISC-V Architecture using FPGA

Consumer electronic computational device requires an efficient system, having minimal Cost and Power Consumption, with high energy efficiency and security. RISCV is a widely accepted Instruction set architecture (ISA) due to its compatibility with direct native hardware implementation rather than simulations and has support for extensive ISA extensions with specialized variants. Bit Manipulation Instructions (BMIs) were introduced by ARM and Intel to improve the runtime efficiency and power dissipation of the program although RISC-V ISA is popular it currently supports only two basic BMIs. This paper presents a simplified architecture of a fully Synthesizable 32-bit processor ”bitRISC” based on the open-source RISC-V (RV32I) ISA and also introduced two new RISC-V BMI's and implemented it on our designed processor, targeted for low-cost Embedded/IoT systems to optimize power, cost and design complexity. The ”bitRISC” is a single cycle processor designed using Verilog HDL and our simplified architecture and is further prototyped on ”ZedBoard” FPGA.