Near Threshold Design Technology Optimization in 12LP Process

Near Threshold Design has become a key design and technology co-optimization area due to a recent explosion of ultra-low power design required for Artificial Intelligence and Machine Learning (AI/ML) for edge devices as well as other Internet of Things (IoT) applications. As we are attempting to operate the design very close to the threshold voltage, significant design and technology challenges need to be addressed before the power and performance benefit can be obtained for these new areas of applications. Accurate model to hardware correlation, technology, device and circuit design co-optimization, advanced library and memory characterization techniques as well as overall sophisticated SOC design methodology are required for this level of product design. Clever and nimble SOC test-chip architecture is essential with many “Design of Experiments” in order to find the design & technology sweet spot. In this paper, we will demonstrate how a smart SOC test-chip architecture together with advanced technology and circuit co-optimization can drive a lowest power solution in Finfet Technology.