Reduction of Harmonic Distortion of 14-nm InAs Quantum Well n-MOSFET for High DC to AC Conversion Efficiency and High Voltage Gain

Using well-calibrated TCAD simulation, we systematically investigate distortion parameters in terms of second order harmonic distortion
$(HD_{2})$
, third order harmonic distortion
$(HD_{3})$
and total harmonic distortion (THD) for InAs quantum well nMOSFETs with raised source/drain architecture having channel thicknesses of 3, 6 and 8 nm at channel length of 14nm by varying angle of grooving
$(\theta)$
from 60° to 90°. Though our findings reveal that total harmonic distortion increases with decreasing thickness and angle of grooving of InAs quantum well device for all
$\mathbf{V}_{\mathbf{GT}}$
, lower values of THD is achieved at higher transconductance generation factor (TGF) with a channel thickness of 3 nm and angle of grooving of 60°. At
$\mathbf{TGF}=5\ \mathrm{V}^{-1}$
, THD is −34 dB for 3 nm thin device which is 5 dB lower than 8 nm thick device at
$\theta=60^{\circ}$
. Maximum reduction in THD of 17 dB is realized for a 3nm thick device compared to 8nm thick device to achieve a fixed voltage gain.