Yield estimation of NCFET-based 6-T SRAM

The key feature of NCFET (negative capacitance field effect transistor) is its sub-threshold slope (SS)
$< \mathbf{60}$
mV/decade at 300 K. In this work, the n-type NCFET (i.e., pull-down (PD) and pass-gate (PG) transistor in SRAM bitcell) has SS of 53.92 mV/decade, and the p-type NCFET (i.e., pull-up (PU) transistor in SRAM bit-cell) has SS of 58.96 mV/decade. In the NCFET-based SRAM cell (vs. conventional SRAM cell with conventional planar bulk MOSFETs), its read (hold)-stability and write-ability are evaluated by the metric of read static noise margin (SNM) and write-ability current
$(\mathbf{I}_{\mathbf{w}})$
, respectively. Then, under process-induced variation, the yield of NCFET-based SRAM array (vs. conventional SRAM array) is quantitatively estimated, using the cell-sigma.