A Survey on Test Point Insertion (TPI) Schemes

With advances in semiconductor technology, device integration density increases resulting in more complex designs with more testing challenges. Limited speed, memory and I/O channels of Automatic Test Equipment (ATE) is a testing challenge. Test power is also a major concern for the reliability of the device. The requirement of fewer test patterns for achieving high test quality and minimizing test time is a challenge in scan-based testing, therefore test point insertion scheme is used to solve these issues at a cost of area and performance overhead. This paper is a study of various test point insertion schemes and analyzing how these test point insertion algorithms have an effect on patterns generation, area, power, test time and fault coverage of a circuit.