A Power Saving Bit-line Keeper for Computational Memory Architecture

The computational Memory Architecture (CMA) supporting in bit-line processing brings parallel computation as close as possible to the location of the stored data without using any dedicated logic unit(s) for computation. It is composed of multiple compute-lines and introduces promising potentials to cope with the growth of Big Data, memory wall and power wall. The controller first selects and sets up an operation, reads bit information from external inputs and/or local memory cells in parallel and simultaneously, stabilizes the bit-lines throughout the controlled bit-line keeper (KEEPER), and finally writes the data to external outputs and/or local memory cells in one compute cycle. Using dedicated topology, connecting inputs and outputs of multiple compute-lines, can specifically help in harnessing the power of CMA in existing research areas such as applications in neural network and/or deep learning. However, the compute-line uses a bit-line keeper control line (BK line) to initiate the bit-line stabilization before any write operation and keeps charging pulled-down bit-lines through a weak voltage supplied by nMOS transistors. Therefore, the compute-line requires extra logic circuitry, delays computation and consumes more energy. In this work, we introduce a power-saving bit-line keeper (P-KEEPER) that reduces power consumption, omits any dedicated commands from the controller, and avoids charging pulled-down bit-lines. This helps in reducing the number of phases in one compute cycle, the power consumption, the compute cycle and the write critical zone by a factor of two, 56.7%, 50.0% and 33.3%, respectively.