Area and Energy Efficient Approximate Square Rooters for Error Resilient Applications

Approximate Computing is gaining momentum for design of accuracy-energy configurable circuits for error-tolerant applications. In this paper, a low power reduced area square root (SQR) circuit is presented that achieves remarkable area and energy efficiency, while introducing trivial inaccuracies in the results. Two approximate designs are proposed for restoring array based square-root circuit for error-resilient applications. In the first design, approximate restoring subtractor cells are used to substitute exact SQR subtractor cells by simplifying the boolean expressions. The second design reduces the design complexity and increases energy efficiency by using the classic approximate computing technique of bit-truncation. Both the designs are implemented for 8- and 16-bit square-root circuit design with different values of approximation parameter ‘d’ for achieving various design trade-off points. Our results indicate that the proposed approximated SQR designs show an improvement in terms of delay, power consumption, energy and area and improves these parameters on average by 37%, 24%, 18%, and 44%, respectively for 16-bit SQR designs when implemented on CMOS 45-nm technology node without compromising much on accuracy. Also, the proposed approximate designs are tested on error tolerant applications including contrast enhancement for medical images and envelope detection in AM (Amplitude Modulation) communication systems. Furthermore, our results validate the approximate square-root designs with improvement in Contrast to Noise ratio (CNR) for image processing applications and an acceptable Signal to Noise ratio (SNR) for analog communication system.