A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors

Modern processors employ a large number of architectural features such as speculative execution and reordering of memory operations to achieve higher performance. Such memory ordering operations are governed by Memory Consistency Models (MCM) which act as an agreement between the programmer and the hardware designer. However, due to a large number of valid execution results, simulation-based verification of an MCM implementation is a difficult task that necessitates its validation after manufacturing. In the first silicon, due to restricted observability, the order of execution of memory operations must be logged on-chip. These logged contents can then be dumped off-line for further constraint graph based analysis and checking for any MCM violation(s). In this paper, we propose a logging-based post-silicon validation of the Total Store Order (TSO) memory consistency model which is widely utilized in modern processors. The logged events capture the ordering of memory operations during the execution of a test program on the processor-under-validation. The main features of the proposed logging approach are zero network traffic overhead along with minimal area, power and performance overheads. Experimental results indicate that the proposed logging approach is effective in detecting the bugs through the constraint graph based checking methodology. The proposed logging approach is implemented both on an architectural simulator and at the register-transfer level in a multi-core out-of-order processor.