Configurable Verification IP for UART

Verification of Integrated Circuits using Verilog lacks the flexibility and reusability of the environment. System Verilog provides building blocks and OOP concepts to work with. That allows to create much more flexible test environment with reusable components. This paper presents a verification architecture of configurable Verification IP for UART interface. The Verification IP presented in this paper provides complete functionality of an operating UART interface and can be used to test any UART device. A functional coverage model has been developed to determine if the verification process covers all possible scenarios or not. Each testcase reports coverage which is later used to analyze the effectiveness of the testcase. Full coverage has been achieved using both random and directed test cases. The coding is done using System Verilog and the simulation is done using VCS.