A 90 μW, 2.5 GHz high linearity programmable delay cell for signal duty-cycle adjustment

In this paper we introduce the design of a 2.5 GHz low power CMOS inverter based 4-bit programmable delay cell with high linearity. The circuit is designed and optimized for the use in high-speed current-steering digital-to-analog converters. The basic architecture consists of a current-starved CMOS inverter delay element and a linear 4-bit digital-to-analog converter providing the reference current for the delay element. In addition, an analog low power pre-distortion circuit has been implemented which is modulating the output current of the DAC to compensate for the inherent nonlinearity of the delay element. Thus, the major drawback of state-of-the-art low power CMOS inverter based delay elements has been significantly mitigated whereas the power consumption is still 25 times less than for shunt-capacitor based architectures with comparable linearity. The delay cell including reference current generation and pre-distortion of the reference current only consumes 90 μW and is therefore well suited for low power applications. The proposed delay cell is implemented along with a CMOS pseudo-random bit sequence (PRBS) generator and a retiming flip-flop for providing a test data sequence at the input. Furthermore, a 50 Ω impedance matched buffer circuit has been implemented to measure the exact undistorted waveforms of the delay element at the output. The system is implemented and fabricated in a 22 nm FD-SOI CMOS process.