Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers

Current generation system-on-chips (SoCs) has been increasing in terms of complexity, resulting in dense global interconnect fabric. Routers are a critical part in neuromorphic SoC fabrics, and the majority of previous works do not focus on in depth verification methodology. This is despite the fact that the number of neurons in neuromorphic computing is at least 1000 times larger than conventional SoCs. Hence, it is very likely that the presented results could be affected by unit level hardware bugs that only surface during the integration phase. Additionally, some neuromorphic routers may consist of asynchronous design units, making verification even more challenging. This paper presents the verification methodology utilized to achieve high coverage in asynchronous neuromorphic routers based on the coverage driven flow, along with assertions, checkers, and scoreboarding for ensuring design correctness. The test plan was developed, beginning with random constrained tests, followed by manually designed directed tests. The combined coverage database of all the simulation runs was able to achieve up to 93% overall coverage, proving the effectiveness of the proposed verification methodology. Furthermore, the methodology was also able to detect bugs early in the design phase, speeding up the entire design flow.