Study on solder void for PiP large solder area ultrathin die in solder reflow

Solder print and reflow is one important process for package assembly, especially for some advanced packages. In Package in Package (PiP) module, the solder void formed between the die and the die attach pad of substrate during solder reflow is very common but difficult to eliminate for large solder area die, it is not only detrimental for package thermal dissipation, power dissipation and signal transmission, but also easy to induce serious assembly issue of die crack, especially for ultrathin die.In this study, the root cause of die crack is identified by failure analysis, and the safe margin of solder void percentage for crack is found out by die stress simulation. By analyzing the mechanism of solder void for both Quad Flat No-lead (QFN) and die with large solder area in PiP, the root cause of solder void is understood. By experiment of solder void, the main effect factors of solder void are found out. By experiment of design(DOE), the process conditions are optimized, the solder void of QFN and die are improved. To further improve the solder void underneath ultrathin die, the secondary print and reflow process is introduced and combined with optimized process conditions by DOE, reduced the solder void coverage to less than 3%, which can solve the die crack issue.