A Parallel Quad Itoh-Tsujii Multiplicative Inversion Algorithm for FPGA Platforms

Modular inversion in GF (2
^m
) is one of the computationally intensive tasks in cryptographic applications like Elliptic Curve Cryptography (ECC). For hardware implementation over binary extended field, Itoh- Tsujii inversion Algorithm (ITA) using sequential multiplication and squaring is considered as the most efficient algorithm. In this paper, we propose a new parallel Quad ITA(QITA) over the National Institute of Standards and Technology (NIST) recommended trinomials to efficiently compute inverse operation on Field-Programmable Gate-Array (FPGA) platforms. Due to the implementation of novel short length addition chain and parallel Quadblock, area-time efficiency has been enhanced in this architecture. This modification allows the computation of inversion with reduced clock cycles comparatively. The experimental results reveal that the proposed parallel QITA algorithm improves the area-time performance as compared to other existing works.