64-bit ALU Design using Vedic Mathematics

The paper provides the details of a 64-bit ALU design based on Vedic Sutras like Urdhva Tiryakbhyam and Nikhilam and implementation results on FPGA. The designed Vedic multiplier obtains results after calculation in 4.014ns time. Xilinx’s Spartan FPGA kit is utilized for realizing the complete ALU module which is coded using Verilog HDL. Simulation results are obtained using Xilinx ISE 12.3 software after thoroughly analyzing multiplication operation. The results show that the vedic sutras are applicable for multiplication operation. The arithmetic module implemented is most efficient in terms of delay reduction by 85% because of vedic sutras.