A One-Cycle Asynchronous FIFO Queue Buffer Circuit

The interfaces of process elements in System-On-Chip (SOC) have become a challenge due to process PVT variations that directly harm the clock distribution from one side; and on the other side, the goal to maintain low cost of clock distribution by obviating the use of clock related circuits; such as, PLL and DLL circuits that are generous for consuming power. The first-in first-out (FIFO) memory with asynchronous separate write/read operation is presented to ease the communication between process elements. The aim is to operate the FIFO without signaling like a clock signal (clockless) in a handshake system signaling protocol. This work proposes an energy-efficient asynchronous (clockless) FIFO memory design that operates on the handshake signaling that is Request and Acknowledge signals. The design generates the Acknowledge signal based on the received Request signal using a new asynchronous circuit that controls the operation of the FIFO. Thus, the design can be considered as a potential technology of choice for low-power applications such as IoT communication solutions. Compared to prior work, our design can operate 5X faster at the same supply voltage. The design’s total power consumption is 2 mW with a total transistor count of 34,470 at 65 nm and 1 V power supply.