Design and Demonstration of a SIMD System Based on the Bit-serial PE Array in FPGA

This study described a new SIMD system architecture based on the bit-serial processor element (PE) array. In order to simplify the PE, the ALU merely has addition/subtraction and logical bit operations. And the unsigned /signed multiplication operations are decomposed into addition and shift operations, based on the booth multiplier principle. The SIMD system includes two decoding modules- the Control Part that filters the ALU instructions and processes the others and the Decoded Part that decodes the ALU instructions, especially the unsigned /signed multiplication instruction. An outline for three plans of multiplication is given and compared to optimize the design. Comprehensively considering the speed and resource utilization, the radix-4 plan was selected for the design and tested. We have experimentally demonstrated the bit processor array with multiplication operation using as few resources as possible.