Implementation of Low Power 1-bit Hybrid Full Adder using 22 nm CMOS Technology

Adders are plays a vital role in digital and vlsi systems. Arithmetic operations are an essential part of digital systems. During VLSI systems, the entire research is on lowering the scale of transistors for enforcing any other digital system. This proposed architecture implemented by different types of logic systems; each logic performs the different role in the hybrid system. The hybrid Full Adder cell with one bit is implemented in this structure. The proposed method is investigated using 22-nm CMOS hybrid full adder. The proposed architecture demonstrates substantial efficiency in power consumption and delay, based on simulation results. The simulation result expressed that the full adder circuit is used to modern high speed central processing unit in the data path architecture. This form of hybrid Full Adder, reduces the delay and increasing efficiency and mainly used in nano technology applications. The average power consumption of 1.1055 μW with moderately low delay of 7.0415ps was found to be extremely low for 0.8-V supply at 22-nm technology. These kind of adder allocates significant improvements in power, high speed and area compared with previous full adder designs.

I. Introduction

Today generation comes from micrometer to nanometer, thus reducing gate length and transistor thickness. Full adders are play a important role in VLSI systems, it improves the performance of digital and nano computing systems. Optimization at all design levels is required to minimize the power Consumption for digital systems. This paper represents the method of development involves the technologies used to implement the digital circuits, the architecture used to implement the circuits, and the algorithms being applied at the highest level. In modern computing applications, the arithmetic units are used to improvise the efficiency of the adder systems.