Towards Implementation of Frame Preemption Mechanism on FPGA Platform

Time Sensitive Networking (TSN) becomes a dominant technology, both in automotive networks and industrial communication systems. Recent amendments to IEEE 802.1 and 802.3 standards, delivered by several TSN working groups, allowed for deterministic and synchronized communication on top of Ethernet infrastructure. One such amendment introduces a frame preemption mechanism, which enables low-priority traffic to be interrupted by time-critical frames of higher priority. In this paper, we describe an implementation of the frame preemption mechanism on a low-cost FPGA (Field-Programmable Gate Array) platform. The functionality of the implemented design has been verified using industry standard tools and the verification results are reported in the paper.