Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits

Monolithic 3D circuits propose new challenges in physical design and optimization, especially during the logical and the physical synthesis steps, due to the vertical structure of active layers, power distribution, thermal behavior, and the high density of devices and interconnects. The technology is not mature yet, and it lacks of automation tools to solve those challenges. We studied the impact of gate sizing in power and delay for pulldown and pull-up networks placed in different active layers and separated by an inter-layer dielectric. Monolithic vias provide the interconnection among layers. Furthermore, we propose a gate sizing method based on the timing analysis of transistor-level monolithic 3D logic cells based on prior analysis. Optimized cells present an average increase in performance of 12% and 6% increase in power consumption, depending on the size of the circuit.