A Two-Port SRAM Cell with Improved Write-Ability and Reduced Leakage Current for Signal Processing Applications

In this paper, a novel two-port seven-transistor (7T) static random access memory (SRAM) cell incorporates assist circuitries is proposed. Among them, the read/write control circuit is employed to process the memory cell failures. During a write operation, this circuit is activated to connect a diode-connected transistor to the source of the drive transistor located close to the write bit line (WBL). Hence, it can provide an efficient solution to the writing `1' issue to improve write operations in this manner. Furthermore, during a read operation, a two-phase reading mechanism is employed to enhance the reading speed and thus avoid unwanted power dissipation. Besides, a pre-charging circuit is designed to pull up the bit line of a selected column to the voltage level V
<sub>DD</sub>
before the read or write operation. Finally, with the standby start-up circuit design, the SRAM cell can quickly switch to the standby mode, and thus reduce leakage current in standby mode. Simulation results for the proposed cell design confirm that the proposed cell provides an efficient solution to the writing `1' issue and leakage current reduction.