25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS

Flip-flops (FFs) are key building blocks in high-performance microprocessors, discrete graphics, and hardware accelerators [1]-[3], where pushing frequency has become increasingly critical due to emerging applications, such as AI, machine learning, autonomous driving and security. Time-borrowing (TB) FFs enable a means to fix outlier max-delay paths by reducing process variation and clock skew/jitter margins, resulting in higher frequency operation [4]. However, use of TB FFs is challenging due to higher power cost and lack of area compatibility with conventional FFs for post-placement insertion. Furthermore, increased design complexity require FFs with scan circuits, utilizing either level-sensitive scan design (LSSD), which grows the area significantly with no delay overhead, or the alternate area-efficient rnux-D scan with higher delay. We present a TB fast mux-D scan FF without scan-mux delay overhead and timing, power, and VMIN characterization circuits fabricated in 10nm CMOS, occupying 0.682mm
²
(Fig. 25.7.7). The fast rnux-D FF achieves: (i) measured rise/fall mean setup time improvement of 17ps/16ps and 19ps/52ps rise/fall mean TB window with 36ps worst-case delay gain for the critical path at 650mV, 25°C; (ii) only 8% energy overhead for single-bit and iso-energy for dual-bit at typical 25% data activity; (iii) 150mVVMIN improvement due to write-back elimination; (iv) single/dual-bit cell area compatibility with mux-D FF for post-placement swapping; and, (v) 7.2% block-level performance gain.