Inexact Addition and Subtraction for the Reconfigurable FIR Filter Implementation using CSD based Common Subexpression Elimination

Inexact computing may be employed to reduce power and area in applications where, a small error in computations, does not affect the performance of the system. This paper proposes inexact half-subtractor and full-subtractor circuits, in which, the error occurs only in 25% of all the input combinations. The area and power of the proposed inexact half-subtractor are found to reduce by 25% and 39.37% respectively, with the error in difference occurring only in one input combination out of four. The area and power of the proposed full-subtractor are reduced by 50% and 71.53% respectively with the error in difference occur only at two input combinations out of eight. The proposed inexact subtractors and adders are used for the implementation of reconfigurable FIR filters using vertical horizontal common subexpression elimination (VHCSE) in the canonical signed digit (CSD) space. The area, power, and cell utilization are analyzed and found to reduce compared to the existing CSD based VHCSE algorithm. The performance of the proposed FIR filter is also analyzed in terms of pass-band ripple and stop-band attenuation and found to be within the tolerable limits.