Design and implementation of Phase Locked Loop on 180nm Technology node

This paper signifies the transient analysis of the PLL and is implemented in cadence tool using 180nm technology node. Frequency is expected to be in GHz range for present communication systems to increase the speed and therefore PLL is designed to produce the frequency in GHz range. The designed PLL consists of Phase frequency detector/Charge pump (PFD/CP), second order Low pass filter (LPF) and Schmitt trigger based current starved voltage controlled oscillator (CSVCO). PLL is designed to achieve a stable frequency output. The designed PLL produces 1.084 GHz with 2.382mW of average power consumption.