I. Introduction
Modern microprocessors enable aggressive hardware virtualization that allows multiple processes to co-locate and temporally execute on the system. These security-critical and ordinary processes interact over their execution for an application to progress. However, these processes suffer from interference channels due to the temporal sharing of processor hardware resources, such as caches, translation look-aside buffers, on-chip networks, and even memory controllers. The execution footprint of processes leaves microarchitecture state vulnerable in these shared hardware resources by means of which an attacker process can infer secret data value(s). Thus, it is imperative to ensure non-interference for guaranteeing robust security across secure and insecure processes. To enable noninterference, various software and hardware based solutions have been proposed in literature. At the software level, process-level isolation (e.g., Intel’s SMAP and KASLR) is traditionally adopted across co-executing processes to guarantee memory isolation. However, it falls short in providing processor security as the hardware resources still remain shared across temporally executing processes [1].