A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU

We demonstrate an ultra-low standby power embedded SRAM with cost effective test screening circuits on 110-nm SoC/MCU. A source bias design technique has been applied to reduce SRAM standby power in the resume standby mode where the stored data is retained. Meanwhile the testing time is increased due to the long pause time to screening the retention failures, because the source bias level will be shifted slightly by small SRAM leakage current. Therefore, a 2-stage test screening method for resume standby mode is newly proposed. It is applied for only low-temperature test loop to minimize the total testing time without any test coverage loss. Test chips including 130kbit SRAMs on 110-nm show full reading and writing operations and 0.28 pW/cell resume standby power at 1.5 V typical supply voltage and 25°C. The testing time is reduced to 1/50 by proposed 2-stage screening testing circuits with only 0.03% area overhead.