High-performance RISC-V processor with improved dispatch and commit schemes

A 2-way superscalar RISC-V processor design with dynamic execution is demonstrated in this paper. The design employs the Gshare scheme for branch prediction and Tomasulo Algorithm for out-of-order execution. The core is capable of speculative execution with five checkpoints and machine-level privileged instructions. Data flow in dispatch and reorder stages is optimized to achieve higher instruction throughput. Different benchmarks of performance are compared with reference work. The design reaches an average improvement of 21.4% on instruction per cycle and improvement of 9.35% on prediction hit rate over the design with similar architecture.