Top-gated atomic precision phosphorous doped silicon single electron transistor with low thermal budget gate dielectric

Exponential increases in semiconductor device density have been accompanied by exponential increases in tooling costs for successive generations. Atomically precise devices (APDs) present a comparatively cheap opportunity to assess future device technologies without the investment required to reach manufacturing scales. However, APDs are not easily integrated into standard workflows and require re-development of common device elements to be compatible with the atomically precise components. APDs prepared in a scanning tunneling microscope (STM) via H desorption lithography [1], [2] produce atomically abrupt dopant profiles, but require a bare silicon surface to start the process and restrict the post-processing thermal budget to ~ 350
^o
C to prevent dopant diffusion. This prohibits including surface dielectrics in advance of dopant incorporation and permits only deposited oxides in post-processing. Here, we demonstrate for the first time a surface gate incorporating widely available atomic layer deposition (ALD) Al
₂
O
₃
oxide with APDs made using H lithography and P doping. Fig. 1 shows a schematic (a), an STM image (b) and an optical image (c) of a single electron transistor (SET) processed using previously described methods for P incorporation and Si cap growth at low temperature (LT) [3]. The ALD gate oxide was deposited at 250°C, followed by electron beam lithography to define the metal gate, and photolithography for contact vias and metal fan-out. The SET, though an unconventional device, provides a straightforward path to analyzing energy scales and electrostatics.