Cryogenic Response of HKMG MOSFETs for Quantum Computing Systems

Hardware implementation of Quantum Processors require monolithic integration of CMOS controller and read-out interface circuits, operating at cryogenic temperatures (1-6K), to enable scale-up of the number of Q-bits and energy-efficient noise-tolerant circuit operation [1] (Fig. 1a). In this work, we investigate the critical role of interface traps near band-edge that affect both the sub-threshold swing (SS) and threshold voltage ( (VTH)) of high-K metal-gate (HKMG) n-channel MOSFETs at cryogenic temperature. We highlight two fundamental mechanisms that contribute to an increase in interface trap capacitance (Cit) that affect both the SS and (VTH) at cryogenic temperatures: (a) the proximity of the surface Fermi-level (EF) to the edge of the conduction band (EC), where the density of interface traps (Dit) is higher, and (b) higher sensitivity of the interface trap response for a given change in EF (Fig. 1b). We developed a physics-based cryo-CMOS transistor model [2], by incorporating multiple discrete interface traps located near HC and show excellent agreement with the experiments. This provides an important step towards optimization of future cryo-CMOS technology necessary for interface circuits in quantum processors.