RRAM-Based In-Memory Computing for Embedded Deep Neural Networks

Deploying state-of-the-art deep neural networks (DNNs) on embedded devices has created a major implementation challenge, largely due to the energy cost of memory access. RRAM-based in-memory processing units (IPUs) enable fully layerwise-pipelined architectures, minimizing the required SRAM memory capacity for storing feature maps and amortizing its access over hundreds to thousands of arithmetic operations. This paper presents an RRAM-based IPU featuring dynamic voltage-mode multiply-accumulate and a single-slope A/D readout scheme with RRAM-embedded ramp generator, which together eliminate power-hungry current-mode circuitry without sacrificing linearity. SPICE simulations suggest that this RRAM-based IPU architecture can achieve an array-level energy efficiency up to 1.2 2b-POps/s/W and an area efficiency exceeding 45 2b-TOps/s/mm
²
.