The Global Interconnect Routing Approach for Reconfigurable System-on-a-Chip

The paper considers a global stage of the hierarchical approach to the interconnect routing for island-style reconfigurable system-on-a-chip. The presented technique can also be applied to the programmable integrated circuits and systems-on-a-chip with the switching blocks included. The approach is based on two fundamentals. The first is the use of the modified PathFinder algorithm for both the global and detailed switching blocks level routing. The second is the construction of the mixed route graph assuming the switching blocks are the "black boxes" with a description of the legal inputs-to-outputs connections for the global level routing. Much attention is paid to the rules of a local graph model of switching blocks and their functional parameterized description in Tcl. The presented methods are demonstrated for the case of two types of switching blocks. The computational experiments results in the CPU time for a flat routing and the hierarchical approach routing time in comparison.