Fault Tolerant Layout Gate Simulation in Microwind

The article describes the implementation of fault-tolerant logic elements based on CMOS transistors. The implementation of reliability topology of the inverter and Schaeffer stroke (logic element NAND2) on the basis of CMOS transistors, as well as a comparative analysis of the characteristics. Based on the results of the comparison, it can be concluded that the increase in reliability has affected the speed and power consumption.