An Approach to Verify Electro-thermal Material Stack-up File Based on Modeling of Poly Resistors with Different Geometry

An approach to verify a material stack-up file used for electro-thermal simulation is presented. The proposed technique compares simulation results of electrical simulation based on already qualified SPICE models that consider self-heating effect and electro-thermal simulation that utilizes the cross-sectional stack-up file. The discrepancy of less than 1% between the simulation results were reached. The test circuits with different resistor geometry were used for verification. They were produced in silicon using 0.13 m SiGe BiCMOS technology. The verified material stack up file were embedded in process design kit and allows designers to perform electro-thermal molding to compute a chip temperature profile that have a close fit to the measurements.