A Broadband CMOS High Efficiency Power Amplifier with Large Signal Linearization

This paper presents an 8 to 12 GHz broadband power amplifier with high linearity and efficiency. Large signal linearization methods are employed to improve the linearity. Sweet point control method is adopted to reduce the intermodulation products, meanwhile the active feedback technique is used to improve the 1-dB compression point. Moreover, an improved broadband matching network is proposed to expand the bandwidth of the power amplifier. The power amplifier is designed in 130 nm CMOS process. Post simulation results show that the power amplifier has an average power gain of 10.6 dB, a max power added efficiency of 29.6%, an output compression point of 13.5 dBm at center frequency, whereas the DC power consumption is only 19.2 mW.