Differential Low Noise Amplifier for S-Band Phased-Array Radar in 0.18-µm CMOS Technology

An S-band differential low noise amplifier (DLNA) is presented and implemented in TSMC 0.18-μm CMOS process for use in the receiver of a phased-array radar. A special layout approach is used in the input matching circuit by integrating two individual inductors together to shrink the chip area while increasing the inductances. The 3-dB gain bandwidth of the two-stage DLNA ranges from 1.9 to 4 GHz (72.41%). The measured gain is about 18.5 dB with an average in-band noise figure of 5.77 dB. The chip area is 0.4672 mm
²
.