Supply Induced Jitter-aware Target Impedance Methodology To Solve Signoff Chip-pkg-pcb Co-design Flow

This paper provides new jitter-aware target impedance methodology to solve the power supply induced jitter challenge of high speed signal integrity. It provides a bidirectional electrical signoff flow between chip designer and package designer. It helps electrical resource allocation of package at early design stage based on jitter-sensitivity induced by supply noise of each IP interface circuit performance. There are multiple examples containing DDR, SERDES interface and DLL/PLL interface. The conventional approach to analyze and simulate multi-interfaces IP circuits at the same time will take a lot of resource and may have non-convergence issue in circuit simulator with power delivery network PKG/PCB. The proposed methodology not only analyzes the jitter induced mechanism by supply noise in multi-interface circuit case by case but also provides advanced target impedance modeling method in frequency domain.