An Efficient Implementation of LED Block Cipher on FPGA

LED is an ultra-lightweight block cipher targeting resource-constrained devices. The current hardware architectures of this cipher utilize large logic area, operate in low frequencies and have low throughput. To improve the trade-offs between area utilization and performance, an iterative round-based architecture of LED block cipher is implemented in this paper. LED algorithm is available in 64-bit and 128-bit key sizes. In this paper, the focus is on the 64-bit key with 64-bit block size. This algorithm is implemented on various Field Programmable Gate Array (FPGA) devices. The design is verified on several Altera and Xilinx devices using Altera Quartus II, ModelSim and Xilinx ISE simulators. Both low-cost and high-end FPGA devices were targeted. Tradeoffs between area and performance were considered, with the optimization for performance. The throughput and maximum operating frequency are benchmarked with the existing literature and better performance is achieved. The results show large improvements in maximum operating frequency and throughput as well as reduction in area utilization compared to recent designs of round-based LED block cipher.