Design of Decoder Using Ternary Inverter

For the conventional binary logic, ternary logic is the best alternative which is trivalent logic. Energy efficiency and reduction in chip area as well as complexity plays an important role in ternary. Nowadays CNTFET device is more significant than the other due to higher channel mobility and also enhanced the ate capacitance. In CMOS, the complexity of an interconnect and chip area is increased as the number of function increases. This paper proposes an approach of using CNTFET to get low power consumption and the high-speed ternary decoder. The basic building blocks for designing of the ternary decoder will be PTI (positive ternary inverter) and NTI (negative ternary inverter). The simulation will show the low power, the high-speed ternary decoder.