Analyzing Two Stage CMOS LNA for Wireless Interconnect

Sooner or later the conventional interconnects used nowadays in high speed performance computing systems are going to put serious performance constraints. As the proportion of CMOS technology scaling and interconnect length scaling differs largely, the interconnect length poses drastic speed limitations on the systems. Hence as technology node scales from 14nm to 7nm shows high improvement on speed on paper but is barely achieved in reality compared to node scaling from 130nm to 90nm. As the speed of operation for HPC systems is in Gb/sec, the power consumption due to conventional interconnect will be higher. The solution to this problem is to use wireless interconnects. The wireless interconnect may be fabricated with on chip wireless transceiver. The on chip antenna and router based architecture may help in reducing those routing delays and also saving chip area. The first block in wireless receiver of wireless interconnect is Low Noise Amplifier (LNA), and this work focuses to design and analyse a CMOS LNA operating at 60 GHz, As most of the HPC systems operate at about 60 GHz. The designed LNA's are compared on the basis of figure of merits.