Optimal Power-Area Polar Decoder Design based on Iterative Decomposition Technique

Polar codes have a very good error correcting capacity compared to turbo and LDPC codes of similar length. They are the first to attain the channel capacity. The aim of the proposed work is to design an Area and Power optimal 2b SC polar decoder exhibiting reduced area and power without degrading the latency by iterative decomposition technique. The targeted performances in decoder architecture are achieved by novel reformulation of F-node, G-node and P-nodes.