Evaluation, optimization, and Enhancement of Chaos Based Reconfigurable Logic Design

Nonlinear dynamics and chaos can be utilized to build reconfigurable and adaptive logic gates. The inherent reconfigurability of these gates has promising security applications. The existing designs of chaos based logic gates have high overhead compared to CMOS gates. In order to make chaos based logic competitive, we need performance metrics to enable optimization of the design. In this work, we propose a metric that will enable circuit designers to optimize the logic gate design based on application specifications. We focus on a particular topology and study how different factors influence its performance and how they can be optimized to reduce overhead. However, the basic idea can be used for chaotic map circuit using other topologies as well. We also propose an enhancement technique to significantly expand the design space which is desirable for security applications.