Resilience versus Energy Tradeoffs of Emerging Device Memory Hierarchies: A Survey and Architecture Exploration

A significant shift from conventional memory stack design to novel architectures is required to reduce the processor-memory speed gap. This transformation will be realized through the deployment of the revolutionary memory technologies. The eDRAM and STT-RAM are among the list of alternative memory solutions. Each of these solutions offer various desired and unwanted characteristics. In this paper, we demonstrate multiple optimization approaches for selecting the optimal memory technology in CMP.