More Accurate Miller Capacitor Modeling for SiC Switching Characteristic Prediction in High Frequency Applications

A more accurate miller capacitor model is proposed in this paper to achieve precise SiC switching characteristic prediction for high frequency and high power density designs. The SPICE models of power transistors are either not provided or fail to represent parasitic capacitor accurately, which will lead to poor estimation of device switching loss. For SiC transistor used in this paper, LTSPICE simulation shows up to 53.7% mismatch in miller capacitor compared with measurement data provided in datasheet. Accurate switching loss prediction will help to use SiC more effectively and thermally optimized in high frequency, high power density systems. The physical mechanism of miller capacitor reflects an internal cascaded configuration of a fixed capacitor with a voltage depended capacitor. The voltage depended capacitance is further influenced by different doping concentrations in vertical power MOSFET and can be splitted into four stages. Based upon these, the Segmented-and-Cascaded miller capacitor approximation method is proposed. It shows descent agreement with datasheet C-V curve of less than 15% mismatch, which is three times less than SiC SPICE model. Experimental results using double pulse test circuit are provided to verify the proposed miller capacitor model. The maximum mismatches under hard switching at 500V are 9.5% for dv/dt and 8.4% for di/dt.