Optimized Multilevel Inverters Derived From Generalized Asymmetrical Topology

Multilevel inverters have become more popular in the recent years for high power-medium voltage applications. Multilevel inverter performance is high compared to the conventional two level inverters due to their reduced harmonic distortion and lower electromagnetic interference. However, the main drawbacks of conventional multilevel inverters are increased number of switches, complex pulse width modulation control and balancing of capacitor voltages. In this paper, a generalized topology for single phase asymmetrical multilevel inverter has been proposed. This generalized topology is optimized to reduce number of switches and to minimize number of switchings per cycle. The optimized topologies have been proposed for five, seven and nine level inverters and a switching strategy is proposed to determine optimum switching angles which give lowest THD at fundamental switching.