A Novel Dynamic PI Simulation Methodology Including Non-linear PMIC Characteristics for DDR5 Module

With the ever-increasing demand for both highperformance and low-power memory modules, it is becoming more and more difficult to meet the SI/PI-related target specifications. This problem can be further aggravated as the supply voltage of Double Data Rate (DDR) memory module decreases from 1.2 V down to 1.1 V for DDR5, possibly resulting in more logic malfunctions of the system. In order to mitigate these problems, Power Management Integrated Circuit (PMIC) is adopted on the DDR5 module to enhance the PI performance. Accordingly, an accurate evaluation of its characteristics has become of utmost importance for prediction of module-level voltage ripple (AC) and IR drop (DC) characteristics. In this paper, a novel methodology for accurate analysis of module-level PI performance, which includes non-linear PMIC characteristics along with other power models of passive components and CPM, is proposed. Through a series of simulations in both time and frequency domains, we successfully verified the accuracy of the proposed methodology and proved its high practicality.